The present invention relates to a semiconductor device and, more particularly, to a semiconductor integrated circuit device in which memory cells are of an I.sup.2 L (which is an abbreviation for Integrated Injection Logic) type.
In general, each of the memory cells of a bipolar memory device comprises a pair of load transistors connected to one word line, and a pair of cross-coupled transistors, connected to the load transistors, to one hold line, and to a pair of bit lines, which serve as a flip-flop. In the bipolar memory cells, the resistance value of the load resistors is designed to be very large so as to reduce the power consumption thereof. Therefore, the area of the load resistors occupied in a chip is very large and, in addition, isolation between the cross-coupled transistors is required. Consequently, the bipolar memory cells are large in size, which results in low integration density and a corresponding high manufacturing cost of the bipolar memory device.
In recent years, an I.sup.2 L memory device has been developed. In an I.sup.2 L memory cell, a pair of load transistors which serve as injectors are used instead of the above-mentioned large load resistors and, to moreover, no isolation between transistors within a row is required. As a result, high integration density and low manufacturing cost can be attained. It should be noted that such an I.sup.2 L memory device can be manufactured by using conventional bipolar technology.
Usually, one I.sup.2 L memory cell comprises first and second transistors of a first conduction type, (such as a pnp), which serve as injectors, cross-coupled third and fourth transistors of a second conduction type, (such as an npn), which serve as a flip-flop, and fifth and sixth transistors of the second conduction type for detecting and reversing the state of the flip-flop, in the read and write mode respectively. The third and fourth transistor are always in the reverse conducting mode, in other words, the emitters and collectors of these transistors are used as collectors and emitters, respectively. In addition, when the memory cell is non-selected, the fifth and sixth transistors are also in the reverse conducting mode. Contrary to this, when the memory cell is selected, the fifth and sixth transistors are in the forward conducting mode.
In the above-mentioned I.sup.2 L memory cell, one of the third and fourth transistors is conductive, while the other is non-conductive. If the third transistor is conductive, injection currents of the first and second transistors are supplied to the collector and base of the third transistor, respectively. In order to change the cell information, the third transistor must be made non-conductive. This is done by supplying an emitter current larger than a write threshold current I.sub.wth, and thus bypassing the base current of the third transistor to the base current of the fifth transistor parallel to the third transistor. In this case, the write threshold current I.sub.wth depends on the total injection current I.sub.inj which flows through a common emitter of the first and second transistors. In other words, when the injection current I.sub.inj is large, the write threshold current I.sub.wth is large.
On the other hand, sink currents, which are explained below, flow from a selected memory cell to non-selected memory cells. The sink currents increase the injection current I.sub.inj of the selected memory cell and, accordingly, increase the write threshold current I.sub.wth, so that the speed of the write operation becomes slow.
In order to decrease the sink currents flowing from a selected memory cell into non-selected memory cells, one conventional I.sup.2 L memory device comprises a clamp circuit. The clamp circuit comprises a plurality of pairs of clamp transistors, pair being connected to one of the pairs of bit lines. In the write mode, a high voltage is applied to the bases of the clamp transistors, so that sink currents flow into non-selected memory cells from the clamp transistors.
However, in a selected column of the above-mentioned conventional device (i.e. the column) in which a pair of bit lines are selected), since a write current I.sub.w is usually much larger than a sink current I.sub.s or a read current I.sub.R, the difference in potential between the selected pair of bit lines is also much larger during the read mode than during the write mode. Therefore, since the speed of the read operation depends on the difference in potential between the selected bit lines, the speed of the read operation of the above-mentioned device becomes slow.